| PART |
Description |
Maker |
| UPD44325092BF5-E33-FQ1 PD44325092B-15 |
4M X 9 QDR SRAM, 0.45 ns, PBGA165
36M-BIT QDRTM II SRAM 2-WORD BURST OPERATION
|
Renesas Electronics Corporation
|
| PD46365092BF1-E40-EQ1 PD46365182BF1-E33Y-EQ1 PD463 |
36M-BIT QDRTM II SRAM 2-WORD BURST OPERATION
|
Renesas Electronics Corporation
|
| PD44165094BF5-E33-EQ3-A PD44165094BF5-E35-EQ3 PD44 |
18M-BIT QDRTM II SRAM 4-WORD BURST OPERATION
|
Renesas Electronics Corporation
|
| CY7C1415BV18-250BZI CY7C1415BV18-167BZI |
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 1M X 36 QDR SRAM, 0.45 ns, PBGA165
36-Mbit QDR™-II SRAM 4-Word Burst Architecture
|
Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
|
| CY7C1514V18 CY7C1514V18-200BZC CY7C1514V18-250BZC |
72-Mbit QDR-II?SRAM 2-Word Burst Architecture
72-Mbit QDR-II(TM) SRAM 2-Word Burst Architecture
72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture
72-MBIT QDR-II⒙ SRAM 2-WORD BURST ARCHITECTURE
72-Mbit QDR-II SRAM 2-Word Burst Architecture
|
CYPRESS[Cypress Semiconductor]
|
| HM66AQB18204BP-33 HM66AQB36104BP-40 HM66AQB9404BP- |
Memory>Fast SRAM>QDR SRAM
36-Mbit QDRTMII SRAM 4-word Burst
|
Renesas Technology / Hitachi Semiconductor
|
| CY7C1313CV18-167BZC CY7C1315CV18-167BZC CY7C1911CV |
18-Mbit QDR垄芒-II SRAM 4-Word Burst Architecture
18-Mbit QDR??II SRAM 4-Word Burst Architecture
18-Mbit QDR?II SRAM 4-Word Burst Architecture
|
Cypress Semiconductor
|
| CY7C1413BV18-300BZXC CY7C1413BV18-300BZXI CY7C1413 |
36-Mbit QDR垄芒-II SRAM 4-Word Burst Architecture
36-Mbit QDR??II SRAM 4-Word Burst Architecture
36-Mbit QDR?II SRAM 4-Word Burst Architecture
|
Cypress Semiconductor
|
| CY7C1515V18-250BZC CY7C1526V18 CY7C1526V18-167BZC |
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture
72-Mbit QDR⑩-II SRAM 4-Word Burst Architecture
72-Mbit QDR?II SRAM 4-Word Burst Architecture
|
CYPRESS[Cypress Semiconductor]
|
| CY7C1250V18-300BZI CY7C1246V18-333BZI CY7C1246V18- |
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 36兆位的DDR - II SRAM2字突发架构（2.0周期读写延迟
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 1M X 36 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
|
| CY7C1314BV18-167BZXC |
18-Mbit QDRII SRAM 2 Word Burst Architecture 512K X 36 QDR SRAM, 0.5 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
